Module grouping to reduce the area of test wrappers in SoCs

DC FieldValueLanguage
dc.contributor.authorKim, Sang-Minko
dc.contributor.authorShin, Youngsooko
dc.date.accessioned2017-12-19T00:57:03Z-
dc.date.available2017-12-19T00:57:03Z-
dc.date.created2017-11-29-
dc.date.issuedACCEPT-
dc.identifier.citationINTEGRATION-THE VLSI JOURNAL, v.60, pp.39 - 47-
dc.identifier.issn0167-9260-
dc.identifier.urihttp://hdl.handle.net/10203/228422-
dc.description.abstractThe number of wrapper cells which need to be added to SoCs for modular testing can be reduced by grouping modules so that they share wrappers. Such grouping may often increase test volume, which can be reduced by redesigning scan-chains and selectively eliminating some wrappers from the input and output ports of grouped modules. In experiments on benchmark circuits, an average of 61% of wrappers were removed when the increase in test time was constrained not to exceed 20%.-
dc.languageEnglish-
dc.publisherELSEVIER SCIENCE BV-
dc.titleModule grouping to reduce the area of test wrappers in SoCs-
dc.typeArticle-
dc.type.rimsART-
dc.citation.volume60-
dc.citation.beginningpage39-
dc.citation.endingpage47-
dc.citation.publicationnameINTEGRATION-THE VLSI JOURNAL-
dc.contributor.localauthorShin, Youngsoo-
dc.description.isOpenAccessN-
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EE-Journal Papers(저널논문)
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