12-bit 100kS/S SAR ADC with 3+9bit segmented CDAC architecture

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Publisher
반도체설계교육센터 (IDEC)
Issue Date
2017-06-29
Language
English
Citation

IDEC SoC Congress Chip Design Contest (ISC)

URI
http://hdl.handle.net/10203/227679
Appears in Collection
EE-Conference Papers(학술회의논문)
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