Models of Clustered Photolithography Tools for Fab-Level Simulation: From Affine to Flow Line

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Fab-level discrete-event simulation is an important practical tool for the analysis and optimization of semiconductor wafer fabricators. In such facilities, a clustered photolithography tool (CPT) is by far the most expensive tool and often the capacity bottleneck. In this paper, we consider linear, affine, flow line, and detailed models of CPTs for use in fab-level simulation. We develop extensions to affine and flow line models and demonstrate exactly how to convert raw CPT data into the various models. Using a detailed CPT model based on industry data as the baseline, numerical experiments are conducted to test the models' fidelity for cycle time, lot residency time, and throughput. We also compare the computational burden of each model class. Further simulations are conducted to test the models' robustness to changing fab conditions, e.g., when lot size or train size changes. Flow line models are shown to be more accurate and robust than linear or affine models and require approximately 200 times less computation than detailed models.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-11
Language
English
Article Type
Article
Keywords

SEMICONDUCTOR WAFER FABS; CYCLE TIME REDUCTION; MANUFACTURING SYSTEMS; FABRICATION; THROUGHPUT

Citation

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.30, no.4, pp.547 - 558

ISSN
0894-6507
DOI
10.1109/TSM.2017.2752755
URI
http://hdl.handle.net/10203/227196
Appears in Collection
IE-Journal Papers(저널논문)
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