DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Jinsu | ko |
dc.contributor.author | Shin, Dongjoo | ko |
dc.contributor.author | Kim, Youchang | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2017-11-20T08:26:05Z | - |
dc.date.available | 2017-11-20T08:26:05Z | - |
dc.date.created | 2017-11-14 | - |
dc.date.created | 2017-11-14 | - |
dc.date.issued | 2017-10 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.10, pp.2714 - 2723 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/227071 | - |
dc.description.abstract | An energy-efficient analog SRAM (A-SRAM) is proposed to eliminate redundant analog-to-digital (A/D) and digital-to-analog (D/A) conversion in mixed-signal systems, such as neuromorphic chips and neural networks. D/A conversion is integrated into the SRAM readout by charge sharing of the proposed split bitline (BL). Also, A/D conversion is integrated into the SRAM write operation with the successive approximation method in the proposed input-output block. Also, a configurable SRAM bitcell array is proposed to allocate the converted digital data without unfilled bitcells. The multirow access decoder selects multiple bitcells in a single column and configures the bitcell array by controlling the BL switches to split BLs. The proposed A-SRAM is implemented using the 65-nm CMOS technology. It achieves 17.5-fJ/bit energy-efficiency and 21-Gbit/s throughput for the analog readout, which are 64% and 1.3 times better than those of the conventional SRAM followed by a digital-to-analog converter (DAC). Also, the area is reduced by 91% compared with the conventional SRAM with analog-to-digital converter (ADC) and DAC. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 17.5-fJ/bit Energy-Efficient Analog SRAM for Mixed-Signal Processing | - |
dc.type | Article | - |
dc.identifier.wosid | 000413751500004 | - |
dc.identifier.scopusid | 2-s2.0-85014263928 | - |
dc.type.rims | ART | - |
dc.citation.volume | 25 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 2714 | - |
dc.citation.endingpage | 2723 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2017.2664069 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Lee, Jinsu | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | ADC | - |
dc.subject.keywordAuthor | analog memory | - |
dc.subject.keywordAuthor | DAC | - |
dc.subject.keywordAuthor | mixed-signal processing | - |
dc.subject.keywordAuthor | SRAM | - |
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