Fully Integrated Digitally Assisted Low-Dropout Regulator for a NAND Flash Memory System

In this paper, a fully integrated digitally assisted lowdropout regulator (LDO) for a NAND flash memory system is proposed and verified using 500 nm I/O CMOSt ransistors. By combining an amplifier (AMP)-based LDO with a comparator (CMP)-based LDO, the proposed LDO achieves both fast load response in the transient state and accurate regulation in the steady state, which are advantages of the CMP-based LDO and AMP-based LDO, respectively. Moreover, loop frequency stability is satisfied in a wide range of load currents between 0 and 150 mA by using the simple structure of the g(m)-boost cell to insert an auxiliary path. For an input voltage range of 2.3-3 V and an output voltage of 2.1 V, the measured output droop is 225 mV for a 150 mA load step in the load transition time of 20 ns with the total bias current of 81 mu A. The fabricated prototype chip occupies 160 x 610 mu m(2) with an on-chip output capacitor of 2 nF.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-01
Language
English
Keywords

LOW-QUIESCENT CURRENT; TRANSIENT-RESPONSE IMPROVEMENT; OUTPUT-CAPACITORLESS LDO; POWER-SUPPLY REJECTION; DC-DC CONVERTER; VOLTAGE REGULATOR; CMOS; DESIGN; AMPLIFIER; BUFFER

Citation

IEEE TRANSACTIONS ON POWER ELECTRONICS, v.33, no.1, pp.388 - 406

ISSN
0885-8993
DOI
10.1109/TPEL.2017.2665476
URI
http://hdl.handle.net/10203/226688
Appears in Collection
EE-Journal Papers(저널논문)
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