DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Seyong | ko |
dc.contributor.author | Lee, HanMin | ko |
dc.contributor.author | Shin, Ji Won | ko |
dc.contributor.author | Kim, Woojeong | ko |
dc.contributor.author | Choi, Taejin | ko |
dc.contributor.author | Paik, Kyung-Wook | ko |
dc.date.accessioned | 2017-10-23T01:30:41Z | - |
dc.date.available | 2017-10-23T01:30:41Z | - |
dc.date.created | 2017-09-25 | - |
dc.date.created | 2017-09-25 | - |
dc.date.issued | 2017-08 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.7, no.8, pp.1258 - 1264 | - |
dc.identifier.issn | 2156-3950 | - |
dc.identifier.uri | http://hdl.handle.net/10203/226314 | - |
dc.description.abstract | 3-D chip-stacking packages and 3-D through silicon via (TSV) vertical interconnection are popular flip-chip assembly methods. Cu-pillar/SnAg micro bumps have usually been used for vertical interconnections in the 3-D TSV chip stacking. These vertical interconnections are fabricated using a thermocompression bonding method with nonconductive films (NCFs). The fabrication heat and pressure lead to molten solder wetting the pad. However, the deformed molten solder on the sidewall of the Cu-pillar results in an increase in solder and Cu-pillar contact interfaces. As a result, more Sn is consumed and Kirkendall voids occur at the solder joint. Novel double-layer NCFs (D-NCFs) can solve the problem of solder wetting the sidewall of the Cu-pillar. D-NCFs are two NCF layers, consisting of a fast-curing top NCF layer and a slower-curing bottom NCF layer. The top NCF layer is designed to have a curing onset temperature below the melting temperature of the solder, to prevent the molten solder wetting the Cu-pillar sidewall. The bottom NCF layer, which has a slower curing property and flux ability, helps the molten solder wet the pads. In this paper, D-NCFs were investigated for the wafer-level (WL) processing of 40-mu m fine-pitch Cu-pillar/SnAg micro bump chip assemblies. The D-NCFs properties were first adjusted for WL capability, and then bonding conditions were optimized in terms of solder wetting on the Cu-pillar and electrical interconnection. As a result, the D-NCFs were found to significantly increase the amount of Sn solder remaining between the Cu-pillar/SnAg/Cu interconnection, and also to decrease Sn consumption. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Wafer-Level Double-Layer Nonconductive Films for Flip-Chip Assembly | - |
dc.type | Article | - |
dc.identifier.wosid | 000409517300008 | - |
dc.identifier.scopusid | 2-s2.0-85028770419 | - |
dc.type.rims | ART | - |
dc.citation.volume | 7 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 1258 | - |
dc.citation.endingpage | 1264 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | - |
dc.identifier.doi | 10.1109/TCPMT.2017.2717440 | - |
dc.contributor.localauthor | Paik, Kyung-Wook | - |
dc.contributor.nonIdAuthor | Kim, Woojeong | - |
dc.contributor.nonIdAuthor | Choi, Taejin | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Component | - |
dc.subject.keywordAuthor | Cu/SnAg bump | - |
dc.subject.keywordAuthor | double layer | - |
dc.subject.keywordAuthor | nonconductive film (NCF) | - |
dc.subject.keywordAuthor | through silicon via (TSV) | - |
dc.subject.keywordAuthor | wafer-level (WL) packaging | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.