Small form factors and high bandwidth are two imperatives nowadays for three-dimensional integrated circuits (3-D-ICs). These requirements can be achieved by the use of through silicon vias, by the reduction of their radius and, at the same time, of the pitch among them. Having a considerable number of devices in a limited space inevitably increases the probability of the creation of defects (short, open, void, etc.). The study of the nature, topology, and creation mechanism of defects is crucial for 3-D-IC design. This paper suggests a procedure able to determine the nature of a defect (open-or short-circuit) and to estimate its position, basing its approach on the study of the electrical parameters of the defected structure, avoiding the use of invasive method such as Lock-in Thermography. A daisy-chain structure is manufactured and open or short defects are intentionally placed along the channel. With and without defects, the equivalent capacitance and inductance are extracted from the S-Parameters, from measurement and three-dimensional electromagnetic simulations, and used to define and validate the proposed procedure.