Localization of Short and Open Defects in Multilayer Through Silicon Vias (TSV) Daisy-Chain Structures

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Small form factors and high bandwidth are two imperatives nowadays for three-dimensional integrated circuits (3-D-ICs). These requirements can be achieved by the use of through silicon vias, by the reduction of their radius and, at the same time, of the pitch among them. Having a considerable number of devices in a limited space inevitably increases the probability of the creation of defects (short, open, void, etc.). The study of the nature, topology, and creation mechanism of defects is crucial for 3-D-IC design. This paper suggests a procedure able to determine the nature of a defect (open-or short-circuit) and to estimate its position, basing its approach on the study of the electrical parameters of the defected structure, avoiding the use of invasive method such as Lock-in Thermography. A daisy-chain structure is manufactured and open or short defects are intentionally placed along the channel. With and without defects, the equivalent capacitance and inductance are extracted from the S-Parameters, from measurement and three-dimensional electromagnetic simulations, and used to define and validate the proposed procedure.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-10
Language
English
Article Type
Article
Keywords

COMPUTATIONAL ELECTROMAGNETICS CEM; SELECTIVE VALIDATION FSV

Citation

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.59, no.5, pp.1558 - 1564

ISSN
0018-9375
DOI
10.1109/TEMC.2017.2685348
URI
http://hdl.handle.net/10203/225970
Appears in Collection
EE-Journal Papers(저널논문)
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