Improving Read Access Time of High-Performance Solid-State Drives via Layered Coding Schemes

Abstract

We study potential enhancement of the read access speed in high-performance solid-state drives (SSDs) by coding, given speed variations across the multiple flash interfaces and assuming occasional local memory failures. Our analysis is based on a queuing model that incorporates both read request failures and node failures. It provides a clear picture on the codingoverhead and read-access-time trade-offs given read failures and node failures. The node failure in the present context reflects various limitations on the memory element level such as page failures, block failures or channel failures that occur during the access of stored data from NAND flash memory chips. A strong motivation for this work is to understand the reliability equirement of NAND chip components given a layer of erasure protection across nodes, under the latency/storageoverhead constraints.