Algorithm for Extracting Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling and Robustness Analysis

This paper explains the extraction from the measurement of the parameters necessary in time domain to identify the hysteretic behavior of the coupling capacitance of through silicon vias (TSVs). The algorithm was developed in such a way that the equivalent capacitance model can be implemented into standard circuit simulators. A comparison with a known procedure based on the genetic algorithm approach is offered as validation. Results showing the robustness of the algorithm and the effects of the hysteresis on the crosstalk among TSV and integrated circuit active devices are reported and discussed.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-08
Language
English
Keywords

COMPUTATIONAL ELECTROMAGNETICS CEM; SELECTIVE VALIDATION FSV; SILICON

Citation

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.59, no.4, pp.1329 - 1338

ISSN
0018-9375
DOI
10.1109/TEMC.2016.2621259
URI
http://hdl.handle.net/10203/223817
Appears in Collection
EE-Journal Papers(저널논문)
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