Write-Amount-Aware Management Policies for STT-RAM Caches

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Spin-transfer torque random access memory (STT-RAM) technology has emerged as one of the most promising memory technologies owing to its nonvolatility, high density, and low-leakage power characteristics. However, STT-RAM has certain drawbacks such as high write energy consumption and limits to the number of write cycles. To enable the adoption of STT-RAM in the implementation of cache memories, new cache hierarchy management policies are required to overcome such drawbacks. In this brief, we evaluated several cache hierarchy management policies in the context of static random access memory L1 caches and an STT-RAM L2 cache. We found that a nonexclusive policy is superior to noninclusive and exclusive policies in terms of energy consumption and endurance. We also propose a sub-block-based management policy because the write energy consumption and endurance are proportional and inversely proportional to the amount of written data, respectively. A combination of the proposed policy with a nonexclusive policy reduces the L2 cache energy consumption by 33.3% (31.5%) and improves the lifetime by 56.3% (56.8%) in a single-core (quad-core) system.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-04
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.4, pp.1588 - 1592

ISSN
1063-8210
DOI
10.1109/TVLSI.2016.2620168
URI
http://hdl.handle.net/10203/223701
Appears in Collection
CS-Journal Papers(저널논문)
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