Signal Integrity Design and Analysis of a Multilayer Test Interposer for LPDDR4 Memory Test With Silicone Rubber-Based Sheet Contact

As the data rate of Low Power Double Data Rate 4 (LPDDR4) memory now exceeds 3.2 Gb/s, it is becoming more difficult to meet the target specifications. While testing has become of utmost importance, it is not viable to have a direct access to the signal pins in a package on package configuration due to the densely located array of solder balls; instead, a test interposer with an excellent electrical performance needs to be adopted to provide test access. In this paper, we first propose a novel test interposer scheme for testing LPDDR4 memory packages. For accurate testing without significant influence on the intrinsic signal path, the proposed test interposer is designed considering a number of signal integrity issues such as intersymbol interference, jitter, impedance matching, and crosstalk. Furthermore, by adopting silicone rubber sheet in place of soldering, the proposed test interposer enhances reusability of the packages with a fast setup time. Moreover, a reconstruction method is proposed that can reconstruct the voltage at application processor using the waveform captured on the test interposer, instead of probing at the ball gray array directly. Through a series of simulations and measurements, we experimentally verified the proposed test interposer. The proposed test interposer scheme can be widely adopted for testing of high-performance packages with its high accuracy and practicality.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-08
Language
English
Keywords

COMPUTATIONAL ELECTROMAGNETICS CEM; SELECTIVE VALIDATION FSV

Citation

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.59, no.4, pp.1239 - 1251

ISSN
0018-9375
DOI
10.1109/TEMC.2016.2639524
URI
http://hdl.handle.net/10203/223642
Appears in Collection
EE-Journal Papers(저널논문)
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