Vertically Integrated Nanowire-Based Zero-Capacitor Dynamic Random Access Memory

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This paper demonstrates a breakthrough for DRAM scaling: A vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell capacitor for data storage, i.e., a zero-capacitor DRAM unlike the conventional DRAM. Vertical integration of the SiNW was attained by a one-route all-dry etching process (ORADEP), resulting in stiction-free stability and simplicity in the fabrication process. High performance that is suitable for high packing density integration is presented with vertically integrated multiple channels, which reveals a potential for an ultimate scaling of DRAM toward the end of the roadmap. (C) The Author(s) 2016.
Publisher
ELECTROCHEMICAL SOC INC
Issue Date
2017
Language
English
Article Type
Article
Keywords

FIELD-EFFECT TRANSISTOR; MOSFETS; PERFORMANCE; 1T-DRAM; CHANNEL

Citation

ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, v.6, no.1, pp.Q1 - Q5

ISSN
2162-8769
DOI
10.1149/2.0011701jss
URI
http://hdl.handle.net/10203/223370
Appears in Collection
EE-Journal Papers(저널논문)
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