Vertically Formed Graphene Stripe for 3D Field-Effect Transistor Applications

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dc.contributor.authorHong, Seul Kiko
dc.contributor.authorBong, Jae Hoonko
dc.contributor.authorCho, Byung-Jinko
dc.contributor.authorHwang, Wan Sikko
dc.date.accessioned2017-04-14T08:16:03Z-
dc.date.available2017-04-14T08:16:03Z-
dc.date.created2016-11-18-
dc.date.created2016-11-18-
dc.date.created2016-11-18-
dc.date.issued2017-01-
dc.identifier.citationSMALL, v.13, no.3-
dc.identifier.issn1613-6810-
dc.identifier.urihttp://hdl.handle.net/10203/223101-
dc.description.abstractA 100-nm wide, vertically formed graphene stripe (GS) is demonstrated for three-dimensional (3D) electronic applications. The GS forms along the sidewall of a thin nickel film. It is possible to further scale down the GS width by engineering the deposited thickness of the atomic layer deposition (ALD) Ni film. Unlike a conventional GS or graphene nanoribbon (GNR), the vertically formed GS is made without a graphene transfer and etching process. The process integration of the proposed GS FETs resembles that of currently commercialized vertical NAND flash memory with a design rule of less than 20 nm, implying practical usage of this formed GS for 3D advanced FET applications.-
dc.languageEnglish-
dc.publisherWILEY-V C H VERLAG GMBH-
dc.titleVertically Formed Graphene Stripe for 3D Field-Effect Transistor Applications-
dc.typeArticle-
dc.identifier.wosid000396567600006-
dc.identifier.scopusid2-s2.0-85002188965-
dc.type.rimsART-
dc.citation.volume13-
dc.citation.issue3-
dc.citation.publicationnameSMALL-
dc.identifier.doi10.1002/smll.201602373-
dc.contributor.localauthorCho, Byung-Jin-
dc.contributor.nonIdAuthorHwang, Wan Sik-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordPlusEDGES-
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