Lithography Defect Probability and Its Application to Physical Design Optimization

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Modern standard cells contain intercell margins at the left and right ends for better lithography. We introduce defect probability, which is the probability that a lithography defect occurs if the margins between two adjacent cells are missing. Computing the defect probability of all cell pairs is impractical due to lengthy lithography simulations and huge number of cell pair combinations. Two approximate methods are employed to make this computation possible: reducing the range of optical proximity correction and grouping cell pairs of similar geometry at the cell boundary. We also present how the cell layout can be modified for a lower defect probability with no impact on the cell electrical parameters. Defect probability is applied to two physical design optimization problems. In the automatic placement, we consider that all cells are initially without margins. We want to locate two cells adjacent if their defect probability is zero (or negligibly small) or insert margins in between; this is achieved using the average defect probability as one of the cost terms of the placement. Experiments in 28-nm commercial library demonstrate an 8% reduction in the area with a 4% shorter wirelength. In the second application, we assume that the standard placement using cells with margins have been performed. We want to identify redundant margins that can be removed while the defect probability is kept zero. We take a step forward and shuffle the location of a few consecutive cells in the same row so that more redundant margins are identified. Once all the redundant margins are removed, newly created whitespace is distributed to reduce routing congestion in highly congested areas. Experiments indicate a 48% reduction in the number of overflow routing grids.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-01
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.271 - 285

ISSN
1063-8210
DOI
10.1109/TVLSI.2016.2572224
URI
http://hdl.handle.net/10203/223097
Appears in Collection
EE-Journal Papers(저널논문)
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