Digitally-intensive RF transmitters for wireless communication systems

Abstract

Increasing demand for applying the concept of soft-defined radio (SDR) to wireless communication systems has focused attention on digital-RF transceiver architecture because digital circuits are generally more reconfigurable and flexible than analog/RF circuits. In addition, digital circuits can be easily transferable to the scaled-down CMOS process and are more preferred with low supply voltage. Furthermore, digital circuits are more robust to PVT variation than analog circuits. The main purpose of this thesis is to implement RF transmitter building blocks in digitally-intensive ways and to avoid the conventional design flow or methodology based on analog circuits in terms of implementing RF transmitters. First, this thesis presents a digital-RF transmitter for a mobile communication standard using multi-bit $\Delta \Sigma$ modulators. Segmented butterfly shufflers with noise-shaped segmentation prevent mismatch errors of digital-to-RF converters from aggravating the linearity of a multi-bit $\Delta \Sigma$ -modulated digital-RF transmitter. A prototype is fabricated in 90-nm CMOS process targeting WCDMA applications. Measurement results demonstrate ACLR (5 MHz/10 MHz) of -49.6 dBc/-53.9 dBc, EVM of 2.78%, and power consumption of 120 mW with a main channel output power of -0.1 dBm centered at 1.95 GHz. Calibration on the I/Q imbalance lowers EVM to 1.7% by improving the image rejection of the transmitter. Next, a CMOS RF digitally-programmable-gain driver amplifier for a RF transmitter of wireless communication standards is presented in this thesis. In order to enhance dynamic range, a digital-step differential attenuator is added in the preceding stage of a DPGA. The prototype fabricated in 0.13- $\mu m$ CMOS technology with 1.2 V of supply voltage achieves 49 dB of dynamic range, satisfying 3GPP specifications of WCDMA. It also features 6.6 dBm of output power with -47.8 dB/-66.2 dB of ACLR1/ACLR2 at 1.95 GHz. Additionally, in the appendix section of this thesis, a CMOS polar transmitter for UHF RFID reader applications is presented. A CMOS PA with a compact spiral-shaped directional coupler for a mobile UHF RFID reader is proposed here and its output power combiner and the directional coupler are implemented using an integrated passive device (IPD) process. The two-chip solution not only enables a CMOS PA to be highly efficient but also allows the directional coupler and the power combiner to be mounted in a compact standard package. A polar transmitter is implemented using the CMOS PA with the directional coupler to verify the operation of the proposed configuration for a UHF RFID reader. Measurements indicate that the peak output power and PAE are 27.9 dBm and 53.7 % for the stand-alone CMOS PA and the CMOS PA with the directional coupler transmits 27.3 dBm of output with 44.6 % of power-added efficiency (PAE). In addition, the implemented polar transmitter with the CMOS PA and the directional coupler satisfies the required UHF RFID reader specifications.