Interface engineering for optimal integration and characteristics of graphene field effect transistors

Abstract

In the past few years, graphene has received much attention for next generation nanoelectronics due to its outstanding electrical properties. Exceptional intrinsic mobilities in graphene combined with the carrier density controllability enables high field effect mobility in graphene field effect transistors (FETs). One significant challenge in realizing graphene nanoelectronics is to integrate graphene into electronic devices. However, it has been reported that the integration of graphene with gate dielectrics and device-compatible substrates is challenging because of several obstacles arising from the inherent properties of graphene, such as the chemical inertness of graphene surface, poor interfacial adhesion and degradation in charge transport property of graphene. Ideally, gate dielectrics for graphene FETs should be directly and uniformly grown on graphene surface with precise controllability of film thickness and ensure the superb charge transport property at dielectric-graphene interface. However, the growth of conformal dielectrics on graphene usually requires additional seed layers or surface treatments via $O_3$ and $NO_2$, which has presented limitations in scaling the gate dielectric thickness or adverse effects in the charge transport properties of the fabricated graphene devices. In addition, utilizing chemical vapor deposition (CVD) that enables large-scale high quality graphene growth requires a transfer step because the growth substrate is not compatible with existing device fabrication procedures. In this thesis, we study novel approaches for achieving optimal integration of graphene with gate dielectrics and device-compatible substrates. For facile and effective transfer of graphene onto a functional device substrate, the mechanism through which the interfacial adhesion property of graphene is affected is systematically analyzed and high quality uniform dry transfer of graphene is achieved. Several materials including poly (4-vinylphenol) (PVP) and functionalized graphene (FG) are newly adopted as an interfacial layer to facilitate the atomic layer deposition (ALD) of high-k dielectrics on graphene. A new method, initiated CVD to form high quality ultrathin polymer dielectric on graphene is also proposed and excellent charge transport property of graphene FET is demonstrated. The results presented here represent optimal methods to integrate graphene into electronic devices, which is a crucial prerequisite for realizing graphene nanoelectronics.