A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that is addressed is to minimize performance loss at NTV or maximize NTV mode clock frequency. A standard cell library for dual-mode circuits is proposed; transistor sizes are balanced and stack transistors are reduced. Gate sizing is performed to minimize negative slacks at both modes; a new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV mode frequency. Clock tree synthesis is re-formulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock path delays themselves, should be made equal. Experiments on test circuits indicate that NTV mode clock frequency is increased by 39% on average; clock skew at NTV decreases by 15% on average. Overall, NTV mode clock frequency is increased on average by 32%, while circuit area and energy consumption is increased by 4% and 5%, respectively.