Synthesis and optimization of dual operational-mode circuits = 듀얼 동작 모드 회로의 합성과 최적화

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A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that is addressed is to minimize performance loss at NTV or maximize NTV mode clock frequency. A standard cell library for dual-mode circuits is proposed; transistor sizes are balanced and stack transistors are reduced. Gate sizing is performed to minimize negative slacks at both modes; a new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV mode frequency. Clock tree synthesis is re-formulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock path delays themselves, should be made equal. Experiments on test circuits indicate that NTV mode clock frequency is increased by 39% on average; clock skew at NTV decreases by 15% on average. Overall, NTV mode clock frequency is increased on average by 32%, while circuit area and energy consumption is increased by 4% and 5%, respectively.
Advisors
Shin, Youngsooresearcher신영수researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2016
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2016.2 ,[viii, 78 p. :]

Keywords

clock tree optimization; dual-mode circuit; gate sizing; near-threshold voltage; timing optimization; 게이트 사이징; 듀얼 모드 회로; 문턱전압 근처 전압; 클럭 트리 최적화; 타이밍 최적화

URI
http://hdl.handle.net/10203/222325
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=648234&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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