Power factor and efficiency improvement of boundary conduction mode boost power factor corrector with digital control based on time domain analysis = 시간 영역 분석에 기반한 디지털 제어를 이용한 임계 도통 모드 부스트 역률 보상 회로의 역률 및 효율 개선

A boost power factor corrector (PFC) is essential in on-line power converters. For efficient electricity usage, it is increasingly required to achieve a high power quality: high power factor (PF) and low total harmonic distortion (THD). Although IEC 61000-3-2 specifies the regulation on PF and THD, it is required to achieve a much higher power quality in the industry. For example, a PF higher than 0.9 at 230Vrms input 20% load condition is an ultimate goal in the 200W TV application. Among many operation modes according to the shape of the inductor current, a boundary conduction mode (BCM) boost PFC is widely used in low-to-mid power applications, because of its low switching loss, simple control, and low cost. However, the power quality of a boost BCM PFC severely decreases as the input voltage increases and the output power decreases. Therefore, in the present situation, it is hard to achieve the industrial goal with a BCM boost PFC. There are two main reasons for this phenomenon. The first one is negative charges and delayed switching period due to the valley switching. The average current of a BCM boost PFC becomes smaller than the ideal amount, due to the negative charges and delayed switching period. The second one is phase leading input current (PLIC) resulted from the input filter capacitor (IFC). A PFC has PLIC because the IFC is connected in parallel with the boost converter. Furthermore, because a BCM boost PFC has high ripple current of the boost inductor, the IFC should be large to reduce EMI noise and voltage stress on the bridge diodes, resulting in a large PLIC on the IFC. Therefore, a large phase difference between the input voltage and current leads to a poor PF and THD. Generally, the additional on time methods can cancel out the effect of the delayed switching period and negative inductor current, because it allows the inductor current to be more built up. Also, because the additional on time methods prevent the switching frequency from increasing near the zero crossing of the AC input voltage, the commercial IC also adopted it. However, a detailed quantitative analysis for the exact additional on time has not been studied till now. Furthermore, the research on compensating the current on IFC in a BCM boost PFC has not been published yet. Nowadays, the digital control of power converters comes into the spotlight, because of its flexible control, reduced components, and no aging problems. In order to beat the limitation of commercial ICs for a BCM boost PFC, several digital control methods based on time domain analysis have been proposed and verified in this dissertation. It is shown that the optimal additional on time should be related to not only the input voltage, but also the output power. According to the analysis, the explicit form of the optimal additional on time has been derived and verified. Also, the effect of the input filter capacitor, which the conventional control methods do not deal with, has been compensated. Therefore, the results from the proposed control methods greatly improved power factor and efficiency compared to any commercial IC. Part 1. A Digitally Controlled Boundary Conduction Mode Boost Power Factor Corrector With Optimized Additional On Time Near the zero-crossing of the input line voltage, an input current distortion and a low PF are caused by delayed switching period and negative input currents. As mentioned before, addi-tional on time method according to the input voltage is used to compensate the input current distortion. However, a detailed quantitative analysis for the exact additional on time has not been studied till now. In this part, the explicit form of the optimized additional on time has been obtained using a quantitative analysis and the advantage of the digital control. From a state trajectory and ‘net input charge’ analysis, it is shown that the optimized on time should be re-lated to not only the input voltage, but also the output power. Also, in order to improve the efficiency in a high input and light load condition, circulating currents are reduced in the inevitable dead angle with a gate turning off technique. By using digital control, the optimized additional on time and the gate turn off technique have been implemented with the $90-230V_{rms}$ input and 380V/200W output prototype. Part 2. Minimizing Effect of Input Filter Capacitor in a Digital Boundary Con-duction Mode Power Factor Corrector Based on Time Domain Analysis Although the average inductor current becomes sinusoidal with the additional on time technique, the power quality of a boost BCM PFC with constant on time decreases both as the input voltage increases and as the output power decreases. With the same input voltage, the power quality decreases as the output power decreases. Also, with the same output power, it decreases as the input voltage increases. The main cause of this tendency can be found from the PLIC phenomenon. Conventional PLIC compensation techniques have focused on a CCM boost PFC. In precedent studies, the causes of PLIC have been investigated by analyzing the current control loop and the input impedance of a boost PFC. However, in a BCM boost PFC, the current flowing through the input filter capacitor becomes a main cause due to its large ripple current. Despite that, there has not been any effort to compensate the current in the IFC in a BCM boost PFC. In this part, a new digital control method is proposed to compensate PLIC in a BCM boost PFC, by minimizing the effect of IFC. The proposed method uses only the derivative of the input voltage, without any additional component. Also, the proposed method improves the displacement factor, but does not affect the distortion factor, resulting in a high power quality in the entire input and output conditions. The derivation of the proposed method is presented based on time domain analysis, and the effectiveness of the proposed method is experimentally verified with a 60Hz 90?230Vrms input and 395V/0.5A output prototype. In this dissertation, the optimized additional on time, the gate turning off technique, and the on time compensation for minimizing the IFC effect have been proposed and verified. The proposed techniques have improved the PF and efficiency of a BCM boost PFC. The final performance of the prototype has the PF higher than 0.9 at $230V_{rms}$ input and 20% load conditions, achieving the industrial goal.
Advisors
Moon, Gun-Wooresearcher문건우researcher
Publisher
한국과학기술원
Issue Date
2016
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2016.2 ,[vii, 140 p. :]

Keywords

boundary conduction mode (BCM); boost power factor corrector (PFC); digital control; additional on time; gate turning off technique; phase leading input current compensation; 임계 도통 모드; 부스트 역률 보상 회로; 디지털 제어; 추가 온 타임; 게이트 오프 기법; 진상 입력 전류 보상

URI
http://hdl.handle.net/10203/222303
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=648238&flag=t
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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