Flash-assisted time-interleaved (FATI) successive approximation (SA) architecture for low power, high speed A/D conversion

Abstract

A flash-assisted time-interleaved SAR ADC architecture has been suggested for high speed A/D conversion. Owing to the MSBs determined by the front end flash ADC, SAR ADC completes the A/D conversion in a reduced number of cycles. Time-interleaved SAR ADCs with a commonly shared low resolution flash ADC provide a new size and power efficient high speed ADC architecture. The proposed ADC structure has been verified by developing a behavioral model of a 6-bit 1.2GHS/s ADC. Circuit design considerations have also been discussed based on the sampling network mismatch between the flash and SAR ADCs. A prototype 6-bit 2GS/s ADC was implemented in a 45 nm CMOS technology. The retire-and-autozeroing scheme was used for a background calibration of comparator offset mismatches. For this, one additional comparator was added in the flash ADC and, also, one additional SAR ADC was inserted in the time interleaving channels. The timing skew mismatch between the flash ADC and SAR ADCs and that between the SAR ADCs were reduced by the clock gating using the global clock and the channel enable signals. The gain mismatches between the ADCs were alleviated by an adequate sampling network design. The ADC core occupies 0.16 mm2 area and consumes 14.4 mW under a 1.2 V supply. With a Nyquist-rate input at a 2GS/s operation, the ADC achieves SNDR of 33.1dB and SFDR of 44.1dB. A peak DNL and INL of the ADC are 0.34LSB and 0.33LSB. The figure of merit (FOM) measured at the Nyquist-rate input is 195fJ/c-step, which is the state-of-the-art class value among the GS/s ADCs with back-ground calibration. A 2x Time-Interleaved FATI SAR ADC with background offset and timing skew calibration is implement in a 45nm and 65nm CMOS. A proposed folding-flash ADC employing designated comparators with dual-sampler and multiple-latches reduces power and hardware burden. Periodic time skew calibration scheme that references a divided external clock is introduced. The operation of the proposed advanced FATI-SAR architecture has been proved by 10-bit 1.6GS/s ADC.