(A) multi-bits per cycle SAR ADC structure for high speed and low power designs = 고속 저전력 디자인을 위한 multi-bits per cycle SAR ADC 구조

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The successive approximation register (SAR) ADCs have been studied because of their power efficient architecture in medium resolution and speed. SAR ADC structure is power and area efficient but is not good at speed. Recently, 2b/cycle SAR ADC architectures have been studied with the aim of enhancing the conversion speed roughly twofold. However, with three SAR ADCs for a 2x speed increase, the 2b/cycle structure suffers from increased hardware overhead. To solve those errors and hardware overhead, design techniques are proposed. Separation of the reference-DAC and the signal-DAC in the proposed 2 b/cycle SAR ADC architecture reduces the number of DACs and saves area and power consumption. The proposed various design techniques such as nonbinary decision, non-latching dynamic register, switching-logic-free DAC control with split-capacitor DAC, and compact layout schemes enhance the ADC conversion speed substantially with excellent low-power performance. The prototype ADC has been implemented in a 45nm CMOS process and the chip operates under 1.1 V for 800 MS/s and 1.25 V for 1 GS/s operation. At the sampling rate of 800 MS/s and 1 GS/s, the chip achieves a peak SNDR of 41.2 dB and 41.8 dB with power consumption of 4.45 mW and 7.18 mW, respectively. The proposed 2b/cycle SAR ADC structure with a 1b/cycle mode change relieves the accuracy requirements of comparators and DACs from the conventional 2b/cycle SAR ADCs while enhancing the ENOB. The timing skew error is greatly reduced by sharing the timing generator for a two-channel interleaved ADC. The prototype design achieves an ENOB of 8.6b in a 9b design at 900 MS/s and a 1.2 V supply with 10.8 mW power consumption. The FOM at the Nyquist rate is 40 fJ/conversion-step. A multi-phase mode change technique with redundancies that disables low-accuracy designed hardware blocks respective to the decision state is proposed to improve power efficiency in multi-bit/cycle architectures, which has been employed to increase the conversion rate of a single channel in alleviating timing skew calibration burdens. The 4x TI 10b prototype design achieves an SNDR of 51.24dB at the Nyquist input, resulting in a FOM of 30.4fJ/conv.-step at 1.7 GS/s conversion rate and 1.2V supply with small area of 0.057mm2.
Advisors
Ryu, Seung-Takresearcher류승탁researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2016
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2016.2 ,[xii, 70 p. :]

Keywords

ADC; 2b/cycle; Multi-bits per cycle; SAR ADC; Time-Interleaved

URI
http://hdl.handle.net/10203/222297
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=648271&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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