Cache and asymmetry aware scheduling for big.LITTLE architecture = 빅리틀 아키텍처를 위한 캐시 및 코어의 비대칭성을 고려한 스케줄링

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Clustered asymmetric multi-cores group big and little cores to different shared cache clusters to further reduce the energy consumption when no big cores are used. However, when all cores are active, prior scheduling schemes for asymmetric multi-cores may no longer be effective with separate shared caches for big or little cores, due the cache sharing and interference effect. This paper investigates whether, for cluster symmetric multi-cores, the cache sharing effect is as important as core asymmetry for scheduling by comparing prior asymmetry-oriented scheduling and cache-oriented scheduling. Since neither cache nor asymmetry-oriented scheduling schemes works best for combinations of applications,this paper proposes a dynamic scheduling scheme based on a hill-climbing algorithm. The experimental results show that the scheduling scheme can improve the overall throughput by 0.9% and 3.5% compared to the prior asymmetry-oriented scheduling schemes.
Advisors
Huh, Jaehyukresearcher허재혁researcher
Description
한국과학기술원 :전산학부,
Publisher
한국과학기술원
Issue Date
2016
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전산학부, 2016.2 ,[v, 27 p. :]

Keywords

Scheduling; Cache; Asymmetry; big.LITTLE Architecture; core; 스케줄링; 캐시; 비대칭; 빅리틀아키텍처; 코어

URI
http://hdl.handle.net/10203/221905
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=649664&flag=dissertation
Appears in Collection
CS-Theses_Master(석사논문)
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