Performance enhancement from patterned interface for planar perovskite solar cells

Abstract

As the rising demand for sustainable energy, inorganic-organic halide perovskite material has been studied actively as photovoltaic material due to its appropriate bandgap energy, ambipolar property, and excellent light absorption as well as easy and cost-effective fabrication process. Most studies have focused on the improvement of perovskite film itself to enhance the performance of the new alternative solar cell. However, in order to improve the overall efficiency of the perovskite solar cell (PSC) device, the role of interlayers, which transport the charge carriers from perovskite layer to electrode is also important and the improvement of the interface property is necessary. In this study, the simple structural modification of the interlayer is demonstrated to improve the device efficiency by larger interfacial area without any adding another interlayer or doping to the existing interlayer. The interfacial modification is achieved by the patterning of poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate)(PEDOT:PSS) hole transport interlayer via polydimethylsiloxane (PDMS) replica stamp patterned by 480nm polystyrene (PS) colloids covered master mold. The pattern of the PEDOT:PSS interlayer shows an ablate hemi-spheroid shape with a height about 45nm and the patterned interface has 8.04% larger interfacial area than the flat interface. The transmittance of the patterned interlayer shows no significant change but the direct circuit (DC) resistance is reduced in compared with the flat interface. With the properties, the larger interfacial area of the patterned interface affects decrease of series resistance and increase of shunt resistance of the PSC device with the patterned interlayer, resulting in improvement of fill factor (FF) by 2.63%. The power conversion efficiency (PCE) of the PSC device with the patterned interlayer is enhanced 3.20% from 17.47% (the flat layer) to 18.10% (the patterned layer) in the case of forward scan. This means that the only structural modification of interface can improve the overall efficiency of the PSC device. The higher performance enhancement of the PSC device with the patterned interface can be achieved by further improvements of the aspect ratio of the pattern such as using hard PDMS stamp and non-close-packed PS colloids array as a master mold.