DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ziabari, Amir Kavyan | ko |
dc.contributor.author | Sun, Yifan | ko |
dc.contributor.author | Ma, Yenai | ko |
dc.contributor.author | Schaa, Dana | ko |
dc.contributor.author | Abellan, Jose L. | ko |
dc.contributor.author | Ubal, Rafael | ko |
dc.contributor.author | Kim, John | ko |
dc.contributor.author | Joshi, Ajay | ko |
dc.contributor.author | Kaeli, David | ko |
dc.date.accessioned | 2017-03-28T06:57:10Z | - |
dc.date.available | 2017-03-28T06:57:10Z | - |
dc.date.created | 2017-02-20 | - |
dc.date.created | 2017-02-20 | - |
dc.date.issued | 2016-12 | - |
dc.identifier.citation | ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, v.13, no.4 | - |
dc.identifier.issn | 1544-3566 | - |
dc.identifier.uri | http://hdl.handle.net/10203/220982 | - |
dc.description.abstract | In this article, we describe how to ease memory management between a Central Processing Unit (CPU) and one or multiple discrete Graphic Processing Units (GPUs) by architecting a novel hardware-based Unified Memory Hierarchy (UMH). Adopting UMH, a GPU accesses the CPU memory only if it does not find its required data in the directories associated with its high-bandwidth memory, or the NMOESI coherency protocol limits the access to that data. UsingUMHwith NMOESI improves performance of a CPU-multiGPU system by at least 1.92x in comparison to alternative software-based approaches. It also allows the CPU to access GPUs modified data by at least 13x faster. | - |
dc.language | English | - |
dc.publisher | ASSOC COMPUTING MACHINERY | - |
dc.subject | DESIGN | - |
dc.subject | ARCHITECTURE | - |
dc.subject | MANAGEMENT | - |
dc.title | UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs | - |
dc.type | Article | - |
dc.identifier.wosid | 000392416400004 | - |
dc.identifier.scopusid | 2-s2.0-85007002393 | - |
dc.type.rims | ART | - |
dc.citation.volume | 13 | - |
dc.citation.issue | 4 | - |
dc.citation.publicationname | ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION | - |
dc.identifier.doi | 10.1145/2996190 | - |
dc.contributor.localauthor | Kim, John | - |
dc.contributor.nonIdAuthor | Ziabari, Amir Kavyan | - |
dc.contributor.nonIdAuthor | Sun, Yifan | - |
dc.contributor.nonIdAuthor | Ma, Yenai | - |
dc.contributor.nonIdAuthor | Schaa, Dana | - |
dc.contributor.nonIdAuthor | Abellan, Jose L. | - |
dc.contributor.nonIdAuthor | Ubal, Rafael | - |
dc.contributor.nonIdAuthor | Joshi, Ajay | - |
dc.contributor.nonIdAuthor | Kaeli, David | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Unified memory architecture | - |
dc.subject.keywordAuthor | memory hierarchy | - |
dc.subject.keywordAuthor | graphics processing units | - |
dc.subject.keywordAuthor | high performance computing | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | MANAGEMENT | - |
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