Low-power dynamic termination scheme using NMOS diode clamping

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An NMOS diode clamped termination (NDCT) with NMOS threshold voltage (V-th) of around 0 V is proposed as a dynamic termination for a high-speed/low-power chip-to-chip interconnection scheme. Both simulation and experimental results for several benchmark circuits show that, compared with open termination, the magnitudes of both overshoot and undershoot for nanosecond-range input pulses are typically less than similar to 15% of supply voltage (V-cc = 3.3 V) with the same order of magnitude in pou er saving, Last, the NDCT is found to be very immune to electrostatic discharge, guaranteeing more than 3000 V for a human body model, Our results demonstrate the potentiality of NDCT as the high-speed interconnection scheme.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
1999-08
Language
English
Article Type
Article
Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.34, no.8, pp.1171 - 1175

ISSN
0018-9200
URI
http://hdl.handle.net/10203/22031
Appears in Collection
EE-Journal Papers(저널논문)
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