Implementation of an 8-channel Statistical Multiplexer8-채널 통계적 다중화기의 구현
본 논문에서는 마이크로프로세서를 이용한 8-channel 통계적 다중화기(SMUX)의 구현에 대하여 기술한다. 하드웨어는 S100-bus 비슷한 bus를 통하여 연결되어 있으며 4MHz clock의 Z-80A 중앙처리장치기판, 프로그램 저장을 위한 16Kbyte LOM기판, data저장을 위한 16Kbyte 동적 RAM 기판 및 세개의 입출력 장치로 구성되어 있다. 이 통계적 다중화기는 50bps에서 9600bps까지의 data를 취급하는 8-channel을 다중화 할 수 있고 한장의 입출력 기판을 제거하고 소프트웨어를 약간 수정하면 4-channel을 수용할 수 있다. 또한 본 장비는 CCITT 권장사항 X.25 link level, V.24, V.28, X.3 및 X.28을 따르고 있다. SMUX 주요특성은 4종류의 입력부호 즉 ASCII, EBCDIC, Baudot, Transcode를 취급할 수 있고 동적 buffer 운영방식과 자체진단 기능을 갖고 있으며, 전체 시스템을 동작시키는데 단지 하나의 CPU를 능률적으로 이용한다는 점이다. 이 시스템의 하드웨어 및 소프트웨어에 관한 자세한 사항은 본론에서 기술한다.
In this paper, we present development of microprocessor-based 8-channel statistical multiplexer(SMUX). The hardware design includes one Z-80A CPU board with the clock rate of 4 MHz, one 16 Kbyte ROM board for program storage, one 16 Kbyte dynamic RAM board and three I/O boards, all connected through an S-100 compatible tristate bus. The SMUX can presently multiplex 8 channels with data rates ranging 50 bps to 9600 bps, but can be reduced to accommodate 4 channels by having a slight modification of software and removing one terminal I/O board. The system specifications meet CCITT recommendations X.25 link level, V.24, V.28, X.3 and X.28. Significant features of the SMUX are its capability of handling 4 input codes (ASCII, EBCDIC, Baudot, Transcode), the use of a dynamic buffer management algorithm, a diagnostic facility, and the efficient use of a single CPU for all system operation. Throughout the paper, detailed explanations are given as to how the hardware and software of the SMUX system have been designed efficiently.
In this paper, we present development of microprocessor-based 8-channel statistical multiplexer(SMUX). The hardware design includes one Z-80A CPU board with the clock rate of 4 MHz, one 16 Kbyte ROM board for program storage, one 16 Kbyte dynamic RAM board and three I/O boards, all connected through an S-100 compatible tristate bus. The SMUX can presently multiplex 8 channels with data rates ranging 50 bps to 9600 bps, but can be reduced to accommodate 4 channels by having a slight modification of software and removing one terminal I/O board. The system specifications meet CCITT recommendations X.25 link level, V.24, V.28, X.3 and X.28. Significant features of the SMUX are its capability of handling 4 input codes (ASCII, EBCDIC, Baudot, Transcode), the use of a dynamic buffer management algorithm, a diagnostic facility, and the efficient use of a single CPU for all system operation. Throughout the paper, detailed explanations are given as to how the hardware and software of the SMUX system have been designed efficiently.
- Publisher
- 대한전자공학회
- Issue Date
- 1984
- Citation
대한전자공학회 논문지, Vol.21, No.5
- ISSN
- 1016-135X
- Appears in Collection
- EE-Journal Papers(저널논문)
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.