Impact of crystalline damage on a vertically integrated junctionless nanowire transistor

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The influence of process-induced defect formation was investigated in a vertically integrated (VI) junctionless-mode field-effect transistor (JL-FET). Compared to the low energy and one-time ion-implantation process to fabricate a single nanowire-based FET, the high-energy and repetitive ion-implantation process for the creation of the VI JL-FET inevitably generates more defects in the crystalline sites. Even after high-temperature rapid thermal annealing, the non-recovered defect sites existing in the interface and silicon channel, as verified by a transmission electron microscopy analysis, lead to the degradation of the electrical performance such as on-and off-state current. Particularly, the abnormal behavior of the off-state current, mostly arising from the gate-induced drain leakage, was analyzed using the experimental results, and supported by the numerical simulation as well. Published by AIP Publishing.
Publisher
AMER INST PHYSICS
Issue Date
2016-10
Language
English
Article Type
Article
Keywords

ULTRA-SHALLOW JUNCTIONS

Citation

APPLIED PHYSICS LETTERS, v.109, no.18

ISSN
0003-6951
DOI
10.1063/1.4965851
URI
http://hdl.handle.net/10203/214217
Appears in Collection
EE-Journal Papers(저널논문)
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