Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures

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Continuous scaling of process technology increases variations in transistors. The process variations cause large fluctuations in the access times of static random-access memory (SRAM) cells. Caches made of those SRAM cells cannot be accessed within the target clock cycle time, which reduces the yield of processors. Many schemes have been proposed to combat these access time failures in caches. However, these schemes are limited in their coverage and do not scale well at high failure rates. We propose a new level one (L1) cache architecture employing multi-cycle cell access (MCCA) and subarray-level parallel access (SLPA). MCCA eliminates all access-time failures in L1 caches. SLPA minimizes the performance impact of cache bandwidth loss due to MCCA. For further performance improvement, architectural techniques are proposed. Our experimental results show that our proposed L1 cache architecture incurs a performance hit of less than 1.2 percent compared to the conventional cache architecture with no access time failure. Our proposed architecture is not sensitive to access time failure rates and has a low overhead compared with previously proposed competitive schemes
Publisher
IEEE COMPUTER SOC
Issue Date
2016-10
Language
English
Article Type
Article
Keywords

LOW-VOLTAGE OPERATION; SENSE AMPLIFIER; YIELD; MICROPROCESSOR; VARIABILITY; WORDLINE; DRAM; DIE

Citation

IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.2999 - 3012

ISSN
0018-9340
DOI
10.1109/TC.2015.2513771
URI
http://hdl.handle.net/10203/213854
Appears in Collection
CS-Journal Papers(저널논문)
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