Vertically Integrated Nanowire-Based Unified Memory

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A vertically integrated nanowire-based device for multifunctional Unified, memory that combine dynamic random access memory (DRAM) and flash memory,,in a single transistor is demonstrated for the first time. The:device Utilizes a gate-all-around (GAA) structure that completely surrounds the nano-wire; the structure is built on a-bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) reliable reproducibility, stiction-free stability, and high-uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified-memory (UM) characteristics. In addition-to-each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing Memory window-than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications
Publisher
AMER CHEMICAL SOC
Issue Date
2016-09
Language
English
Article Type
Article
Citation

NANO LETTERS, v.16, no.9, pp.5909 - 5916

ISSN
1530-6984
DOI
10.1021/acs.nanolett.6b02824
URI
http://hdl.handle.net/10203/213773
Appears in Collection
EE-Journal Papers(저널논문)
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