A Low-Power TDC-Configured Logarithmic Resistance Sensor for MLC PCM Readout

Abstract

This paper proposes a low-power logarithmic resistance sensor for multi-level cell phase-change memory read-out. The proposed sensor is composed of a resistance-to-current converter (R2I) and a current-to-digital converter (I2D). A simple bleeding current source pair added to the R2I enhances the current settling speed and the sensing accuracy. The two-step I2D with a time-to-digital converter-configured fine ADC could be designed with low-power consumption and small size owing to the time-reference generator that is shared by multiple channels and incorporates interpolation and size-scaling techniques. The total conversion time of the readout sensor, including the R2I conversion, is 100 ns, and the power consumption of a single-channel readout sensor is 60 mu W under a 1.2 V supply. The ratio of the minimum decision step size to the full scale input current of the I2D corresponds to that of a conventional 9.6-b linear ADC. The prototype sensor is composed of 14-channels sharing a single time-reference generator, where each narrow single channel occupies 19 mu m x 590 mu m in a 65-nm CMOS process