Wakeup scheduling and its buffered tree synthesis for power gating circuits

Power gating circuit suffers from large amount of rush current during wakeup, especially when all switch cells are turned on simultaneously. If each switch cell is turned on at a different time, rush current can be reduced. It is shown in this paper that rush current can be reduced even more if signal transition time (or signal slew) to each switch cell is adjusted. We define wakeup scheduling as to determine turn-on time and signal slew of each switch cell; the goal is to minimize wakeup delay while keeping rush current below the maximum value that is allowed. The determined turn-on time and signal slew are implemented using a buffered tree. The wakeup scheduling and buffered tree construction are integrated into a design flow. To adapt to process variation, we use adjustable delay buffers in the wakeup network. We also apply grid-based design flow and use Schmitt triggers to implement large designs. Experiments in an industrial 1.1 V, 32-nm technology demonstrate that the wakeup delay is reduced by 12% on average of example circuits compared with turn-on scheduling. (C) 2016 Elsevier B.V. All rights reserved.
Publisher
ELSEVIER SCIENCE BV
Issue Date
2016-03
Language
ENG
Keywords

DESIGNS; VOLTAGE

Citation

INTEGRATION-THE VLSI JOURNAL, v.53, pp.157 - 170

ISSN
0167-9260
DOI
10.1016/j.vlsi.2015.12.008
URI
http://hdl.handle.net/10203/209059
Appears in Collection
EE-Journal Papers(저널논문)
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