DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, Chao | ko |
dc.contributor.author | Zhou, Jun | ko |
dc.contributor.author | Weerasekera, Roshan | ko |
dc.contributor.author | Zhao, Bin | ko |
dc.contributor.author | Liu, Xin | ko |
dc.contributor.author | Royannez, Philippe | ko |
dc.contributor.author | Je, Minkyu | ko |
dc.date.accessioned | 2016-06-29T02:08:31Z | - |
dc.date.available | 2016-06-29T02:08:31Z | - |
dc.date.created | 2016-04-07 | - |
dc.date.created | 2016-04-07 | - |
dc.date.created | 2016-04-07 | - |
dc.date.created | 2016-04-07 | - |
dc.date.issued | 2015-01 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.1, pp.139 - 148 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/208515 | - |
dc.description.abstract | "This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan switch network (SSN) architecture is proposed to perform pre-bond TSV scan testing in test mode, and operate as functional circuit in functional mode, respectively. In the SSN, novel test structures and circuits are proposed to address pre-bond TSV test accessibility issue and perform stuck-at-fault tests and TSV tests. By exploiting the inherent RC delay characteristics of TSV, a novel delay-based TSV test method is also proposed to map the variation of TSV-to-substrate resistance due to TSV defects to a test path delay change. Compared with state-of-art methods, the proposed BIST methodology addresses pre-bond TSV testing with a low-overhead integrated test solution which is compatible to existing 2D-IC testing method. The proposed BIST architecture and method can be implemented by standard DFT design flow and integrated into a unified pre-bond TSV test flow. Experiment results and robustness analysis are presented to verify the effectiveness of the proposed self-test methodology, architecture, and circuits." | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems | - |
dc.type | Article | - |
dc.identifier.wosid | 000347706500015 | - |
dc.identifier.scopusid | 2-s2.0-85027922476 | - |
dc.type.rims | ART | - |
dc.citation.volume | 62 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 139 | - |
dc.citation.endingpage | 148 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2014.2354752 | - |
dc.contributor.localauthor | Je, Minkyu | - |
dc.contributor.nonIdAuthor | Wang, Chao | - |
dc.contributor.nonIdAuthor | Zhou, Jun | - |
dc.contributor.nonIdAuthor | Weerasekera, Roshan | - |
dc.contributor.nonIdAuthor | Zhao, Bin | - |
dc.contributor.nonIdAuthor | Liu, Xin | - |
dc.contributor.nonIdAuthor | Royannez, Philippe | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | BIST | - |
dc.subject.keywordAuthor | DFT | - |
dc.subject.keywordAuthor | pre-bond TSV testing | - |
dc.subject.keywordAuthor | TSV | - |
dc.subject.keywordAuthor | 3D IC | - |
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