DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Insup | ko |
dc.contributor.author | Kim, Jae Joon | ko |
dc.contributor.author | Lin, Yu Shiang | ko |
dc.contributor.author | Shin, Youngsoo | ko |
dc.date.accessioned | 2016-06-07T09:00:07Z | - |
dc.date.available | 2016-06-07T09:00:07Z | - |
dc.date.created | 2015-11-23 | - |
dc.date.created | 2015-11-23 | - |
dc.date.issued | 2016-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.600 - 612 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/207674 | - |
dc.description.abstract | One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction technique imposes a one-cycle time penalty only, but it is restricted to two-phase transparent latch-based pipelines. We perform one-cycle error correction by gating only the main latch in each stage of the pipeline that precedes a failed stage. This new method is applicable to widely used clocking elements, such as flip-flops and pulsed latches. Because it prevents inputs arriving at a stage, which is stalled, it can also be used in pipelines with multiple fan-in, fan-out, and looping. Simulations show an energy saving of 8%-12% with a target throughput of 0.9 instructions per cycle, and 15%-18% when the target is 0.8. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DYNAMIC VARIATION TOLERANCE | - |
dc.subject | POWER | - |
dc.subject | MICROPROCESSOR | - |
dc.subject | VOLTAGE | - |
dc.subject | SYSTEM | - |
dc.title | One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements | - |
dc.type | Article | - |
dc.identifier.wosid | 000369479500017 | - |
dc.identifier.scopusid | 2-s2.0-84925872430 | - |
dc.type.rims | ART | - |
dc.citation.volume | 24 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 600 | - |
dc.citation.endingpage | 612 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2015.2409118 | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.contributor.nonIdAuthor | Kim, Jae Joon | - |
dc.contributor.nonIdAuthor | Lin, Yu Shiang | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Error correction | - |
dc.subject.keywordAuthor | low-voltage operation | - |
dc.subject.keywordAuthor | timing speculation | - |
dc.subject.keywordPlus | DYNAMIC VARIATION TOLERANCE | - |
dc.subject.keywordPlus | POWER | - |
dc.subject.keywordPlus | MICROPROCESSOR | - |
dc.subject.keywordPlus | VOLTAGE | - |
dc.subject.keywordPlus | SYSTEM | - |
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