One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements

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One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction technique imposes a one-cycle time penalty only, but it is restricted to two-phase transparent latch-based pipelines. We perform one-cycle error correction by gating only the main latch in each stage of the pipeline that precedes a failed stage. This new method is applicable to widely used clocking elements, such as flip-flops and pulsed latches. Because it prevents inputs arriving at a stage, which is stalled, it can also be used in pipelines with multiple fan-in, fan-out, and looping. Simulations show an energy saving of 8%-12% with a target throughput of 0.9 instructions per cycle, and 15%-18% when the target is 0.8.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2016-02
Language
ENG
Article Type
Article
Keywords

DYNAMIC VARIATION TOLERANCE; POWER; MICROPROCESSOR; VOLTAGE; SYSTEM

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.600 - 612

ISSN
1063-8210
DOI
10.1109/TVLSI.2015.2409118
URI
http://hdl.handle.net/10203/207674
Appears in Collection
EE-Journal Papers(저널논문)
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