An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs

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An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathematical proof of the algorithm is presented for both rotator-based and VCO-based CDRs with finite loop delay. A 25 Gb/s transceiver IC is fabricated using a 40 nm CMOS process to validate the performance of the algorithm. The power consumptions of TX and RX are 37.8 mW and 46.8 mW, respectively and the synthesized area implementing a digital loop filter together with the proposed ALGC occupies 140 mu m x 170 mu m.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2015-12
Language
English
Article Type
Article
Keywords

ADAPTIVE DELTA-MODULATION

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.12, pp.2817 - 2828

ISSN
1549-8328
DOI
10.1109/TCSI.2015.2495725
URI
http://hdl.handle.net/10203/205720
Appears in Collection
EE-Journal Papers(저널논문)
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