DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Byung Hyun | ko |
dc.contributor.author | Kang, Min Ho | ko |
dc.contributor.author | Ahn, Dae Chul | ko |
dc.contributor.author | Park, Jun Young | ko |
dc.contributor.author | Bang, Tewook | ko |
dc.contributor.author | Jeon, Seung Bae | ko |
dc.contributor.author | Hur, Jae | ko |
dc.contributor.author | Lee, Dongil | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2016-04-22T07:48:07Z | - |
dc.date.available | 2016-04-22T07:48:07Z | - |
dc.date.created | 2015-11-22 | - |
dc.date.created | 2015-11-22 | - |
dc.date.created | 2015-11-22 | - |
dc.date.issued | 2015-12 | - |
dc.identifier.citation | NANO LETTERS, v.15, no.12, pp.8056 - 8061 | - |
dc.identifier.issn | 1530-6984 | - |
dc.identifier.uri | http://hdl.handle.net/10203/205717 | - |
dc.description.abstract | A vertically integrated multiple channel-based field-effect transistor (PET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling. | - |
dc.language | English | - |
dc.publisher | AMER CHEMICAL SOC | - |
dc.title | Vertically Integrated Multiple Nanowire Field Effect Transistor | - |
dc.type | Article | - |
dc.identifier.wosid | 000366339600041 | - |
dc.identifier.scopusid | 2-s2.0-84949563272 | - |
dc.type.rims | ART | - |
dc.citation.volume | 15 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 8056 | - |
dc.citation.endingpage | 8061 | - |
dc.citation.publicationname | NANO LETTERS | - |
dc.identifier.doi | 10.1021/acs.nanolett.5b03460 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Kang, Min Ho | - |
dc.contributor.nonIdAuthor | Ahn, Dae Chul | - |
dc.contributor.nonIdAuthor | Bang, Tewook | - |
dc.contributor.nonIdAuthor | Lee, Dongil | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | silicon nanowire (SiNW) | - |
dc.subject.keywordAuthor | gate-all-around (GAA) | - |
dc.subject.keywordAuthor | vertical integration | - |
dc.subject.keywordAuthor | field-effect transistor (FET) | - |
dc.subject.keywordAuthor | three-dimensional nonvolatile memory | - |
dc.subject.keywordAuthor | one-route all-dry etch | - |
dc.subject.keywordPlus | CMOS TECHNOLOGY | - |
dc.subject.keywordPlus | MOSFETS | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | NM | - |
dc.subject.keywordPlus | DIAMETER | - |
dc.subject.keywordPlus | DESIGN | - |
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