DSpace at KOASAS: A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

DSpace at KOASAS

College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

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Hong, Hyeok-Ki / Kang, HW / Jo, DS / Lee, DS / You, YS / Lee, YH / Park, HJ / Ryu, Seung-Tak researcher

Publisher: IEEE

Issue Date: 2015-02-25

Language: English

Citation: International Solid-State Circuits Conference (ISSCC)

URI: http://hdl.handle.net/10203/204564

Appears in Collection: EE-Conference Papers(학술회의논문)

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A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

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