A DC-to-12.5Gb/s 4.88mW/Gb/s All-rate CDR with a single LC VCO in 90nm CMOS
The proposed CDR supports reference-less all-rate operation with static fractional divider and asynchronous phase calibration scheme. And the IC features an automatic loop gain control scheme which adjusts the bandwidth of a CDR automatically in the background for optimum BER performance. The power efficiency of the test chip is 4.88mW/Gb/s.
- Publisher
- IEEE
- Issue Date
- 2015-09-29
- Language
- English
- Citation
IEEE Custom Integrated Circuits Conference (CICC) 2015, pp.1 - 4
- ISSN
- 0886-5930
- Appears in Collection
- EE-Conference Papers(학술회의논문)
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