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Results 11-20 of 60 (Search time: 0.003 seconds).

NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
11
Factors Affecting Charge-up in a Magnetically Enhanced RIE Polysilicon Etcher

Hyung-Cheol Shinresearcher, Proc. Electrochemical Society, pp.405 - 406, 1993

12
Effects of S/D Non-Overlap and High-k Dielectrics on Nano CMOS Design

Hyung-Cheol Shinresearcher, ISDRS, pp.661 - 664, 2001

13
Thin Oxide Damage by Plasma Etching and Ashing Processes

Hyung-Cheol Shinresearcher, Proc. IEEE International Reliability Phys. Symp., pp.37 - 41, 1992

14
Characterization of Process-Induced Damage During Aluminum Etching and Photoresist Ashing

Hyung-Cheol Shinresearcher, International Wafer Level Reliability Workshop, pp.133 - 144, 1991

15
A nano-structure Memory with SOI Edge channel and A nano dot

Hyung-Cheol Shinresearcher, MNC(Microproceses and Nanotechnology Conference), pp.315 - 316, 1998

16
Recessed Channel(RC) SOI NMOSFET's with Self-Aligned Polysilicon Gate Formed on the RC Region

Hyung-Cheol Shinresearcher, Proc. IEEE International SOI Conference, pp.122 - 123, 1996

17
A Simple Technique to Measure Generation Lifetime in Partially Depleted SOI MOSFETS

Hyung-Cheol Shinresearcher, 5th International Conference on VLSI and CAD, pp.55 - 59, 1997

18
Process-Induced Charging Damage in PETEOS for Interlevel Dielectric Applications

Hyung-Cheol Shinresearcher, International Symposium on Plasma Process-Induced Damage, pp.109 - 112, 1996

19
Comparison of the characteristics of tunneling oxide and tunneling ON for P-channel Nano-crystal Memory

Hyung-Cheol Shinresearcher, The 6th International Conference on VLSI and Cad(ICVC'99), pp.233 - 236, 1999

20
Silicon MOS Memory with self-aligned Quantum Dot on Narow Channel

Hyung-Cheol Shinresearcher, ICVC99, pp.187 - 189, 1999

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