A Distributed Model for Border Traps in Al2O3 - InGaAs MOS Devices

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A distributed border trap model based on tunneling between the semiconductor surface and trap states in the gate dielectric film is formulated to account for the observed frequency dispersion in the capacitance and conductance of Al2O3/InGaAs MOS devices biased in accumulation. The distributed circuit model is more physical and descriptive than previous lumped circuit border trap models in the literature. The distributed model correctly depicts the frequency dependence of both capacitance and conductance data in accumulation. A border trap volume density is extracted from the quantitative agreement with measured data.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2011-04
Language
English
Article Type
Article
Citation

IEEE ELECTRON DEVICE LETTERS, v.32, no.4, pp.485 - 487

ISSN
0741-3106
DOI
10.1109/LED.2011.2105241
URI
http://hdl.handle.net/10203/201689
Appears in Collection
MS-Journal Papers(저널논문)
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