DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, Eun-Seok | ko |
dc.contributor.author | Koo, Kyoung-Choul | ko |
dc.contributor.author | Pak, Jun-So | ko |
dc.contributor.author | Kim, Joung-Ho | ko |
dc.date.accessioned | 2015-11-20T10:19:38Z | - |
dc.date.available | 2015-11-20T10:19:38Z | - |
dc.date.created | 2012-12-03 | - |
dc.date.created | 2012-12-03 | - |
dc.date.issued | 2013-09 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.3, no.9, pp.1467 - 1480 | - |
dc.identifier.issn | 2156-3950 | - |
dc.identifier.uri | http://hdl.handle.net/10203/201330 | - |
dc.description.abstract | In this paper, a new decoupling capacitor stacked chip (DCSC) based on extra decoupling capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth limitation of the conventional decoupling capacitor solutions in three-dimensional-integrated circuits (3-D-ICs), as exhibited by expensive on-chip metal-oxide-semiconductor (MOS) decoupling capacitors and inductive off-chip discrete decoupling capacitors. In particular, in comparison to the on-chip decoupling solutions, such as MOS, metal-insulator-metal and deep trench capacitors, the proposed TSV-based DCSC represents several advantages, such as small leakage currents, large capacitances ranging from tens of nF to a few mu F, low equivalent series inductance (ESL) with tens of pH, and high flexibility in TSV arrangements. The proposed TSV-based DCSC can be applied by mounting decoupling capacitors, such as Si-based MOS capacitors and discrete capacitors, on the backside of a chip and connecting the capacitors to the on-chip power delivery network (PDN) through TSVs. To demonstrate the performance of the proposed DCSC structure, a segmentation method was applied to compare the PDN impedance (Z11) of the TSV-based DCSC with those of the well-known conventional decoupling capacitor methods. The TSV-based DCSC was found to exhibit the advantages of both low on-chip level ESL (under several tens of pH) and high off-chip level capacitance (up to several mu F). Additionally, the PDN impedance properties of the TSV-based DCSC were analyzed with respect to the variations in the number of power/ground TSV pairs, on-chip PDN size, and capacitance values of the stacked off-chip discrete decoupling capacitors using the segmentation method. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | TSV | - |
dc.subject | SUPPRESSION | - |
dc.subject | PACKAGE | - |
dc.subject | TECHNOLOGY | - |
dc.subject | IMPEDANCE | - |
dc.subject | DESIGN | - |
dc.subject | MODEL | - |
dc.title | Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs | - |
dc.type | Article | - |
dc.identifier.wosid | 000324384600004 | - |
dc.identifier.scopusid | 2-s2.0-84884287901 | - |
dc.type.rims | ART | - |
dc.citation.volume | 3 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 1467 | - |
dc.citation.endingpage | 1480 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | - |
dc.identifier.doi | 10.1109/TCPMT.2013.2257928 | - |
dc.contributor.localauthor | Kim, Joung-Ho | - |
dc.contributor.nonIdAuthor | Song, Eun-Seok | - |
dc.contributor.nonIdAuthor | Pak, Jun-So | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | 3-D integrated circuit (3-D-IC) | - |
dc.subject.keywordAuthor | decoupling capacitor | - |
dc.subject.keywordAuthor | decoupling capacitor stacked chip (DCSC) | - |
dc.subject.keywordAuthor | deep trench (DT) capacitor | - |
dc.subject.keywordAuthor | low equivalent series inductance (ESL) | - |
dc.subject.keywordAuthor | off-chip discrete decoupling capacitor | - |
dc.subject.keywordAuthor | on-chip NMOS capacitor | - |
dc.subject.keywordAuthor | power distribution network (PDN) | - |
dc.subject.keywordAuthor | power/ground noise | - |
dc.subject.keywordAuthor | power integrity | - |
dc.subject.keywordAuthor | self-impedance (Z11) | - |
dc.subject.keywordAuthor | stacking | - |
dc.subject.keywordAuthor | simultaneous switching noise (SSN) | - |
dc.subject.keywordAuthor | through-silicon-via (TSV) | - |
dc.subject.keywordPlus | TSV | - |
dc.subject.keywordPlus | SUPPRESSION | - |
dc.subject.keywordPlus | PACKAGE | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | IMPEDANCE | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | MODEL | - |
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