Controlled Wafer Release in Clustered Photolithography Tools: Flexible Flow Line Job Release Scheduling and an LMOLP Heuristic

Abstract

As a clustered photolithography tool (CPT) in semiconductor wafer manufacturing can cost as much as US$100 million, it must be operated efficiently. To maximize throughput, wafers are generally admitted to a CPT opportunistically, that is, as soon as they are available and the tool can accept them. Here, our goal is to develop release methods that retain throughput but increase manufacturing agility. As Petri net methods prove intractable, we develop a heuristic based on the use of flexible flow line models for the CPT. Such models are appropriate when the tool throughput for each class of wafers is dictated by the bottleneck process time plus unavoidable robot handling overhead. The heart of the heuristic is a lexicographic multiple objective linear program (LMOLP). It first ensures that wafers exit the tool as early as possible and subsequently delays the wafer admission to minimize the mean residency time. To test the efficacy of the release policy, we conduct numerical experiments on detailed CPT models based on industry data. The model includes many features of real world tools such as wafer transport robots, an industry-based robot scheduling policy, a prescan track buffer, reticle setups, and track setups. As compared to the commonly used opportunistic wafer admission, the heuristic provides statistically indistinguishable throughput with significant reductions in wafer residency time, in-tool buffer occupation, and hot lot cycle time. We conduct a numerical robustness study to assess the performance of the release policy when the system model used in the LMOLP deviates significantly from the behavior in the CPT. The LMOLP heuristic continues to perform well in the presence of such disturbances. Note to Practitioners-In clustered photolithography tools (CPTs) in semiconductor wafer manufacturing, wafers are commonly admitted to the tool as soon as the wafer handling robot can receive one. While this is done to ensure maximum throughput, it can result in long wafer residency in the tool and a reduction in the ability to promptly serve arriving hot lots. Here, we develop a computationally tractable and practical linear programming based method to obtain more judicious wafer admission times. Detailed simulation studies of models of real CPTs demonstrate no loss of throughput and a 52%, 31%, and 23% improvement in wafer time in the tool, lot time in the tool and hot lot cycle time, respectively. The results are robust; when the CPT exhibits behaviors significantly different than assumed in the controller, the release policy continues to perform well. As such, the method may prove useful in practical contexts to reduce wafer residency time and increase CPT agility.