A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU

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Digital circuits are expected to increasingly suffer from more hard faults due to technology scaling. Especially, a single hard fault in ALU (Arithmetic Logic Unit) might lead to a total failure in processors or significantly reduce their performance. To address these increasingly important problems, we propose a novel cost-efficient fault-tolerant mechanism for the ALU, called LIZARD. LIZARD employs two half-word ALUs, instead of a single full-word ALU, to perform computations with concurrent fault detection. When a fault is detected, the two ALUs are partitioned into four quarter-word ALUs. After diagnosing and isolating a faulty quarter-word ALU, LIZARD continues its operation using the remaining ones, which can detect and isolate another fault. Even though LIZARD uses narrow ALUs for computations, it adds negligible performance overhead through exploiting predictability of the results in the arithmetic computations. We also present the architectural modifications when employing LIZARD for scalar as well as superscalar processors. Through comparative evaluation, we demonstrate that LIZARD outperforms other competitive fault-tolerant mechanisms in terms of area, energy consumption, performance and reliability.
Publisher
IEEE COMPUTER SOC
Issue Date
2015-09
Language
English
Article Type
Article
Keywords

MICROPROCESSOR; RELIABILITY; REDUNDANCY

Citation

IEEE TRANSACTIONS ON COMPUTERS, v.64, no.9, pp.2433 - 2446

ISSN
0018-9340
DOI
10.1109/TC.2014.2366743
URI
http://hdl.handle.net/10203/200436
Appears in Collection
CS-Journal Papers(저널논문)
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