Showing results 9181 to 9200 of 50972
Arbitrary-ratio image resizing using fast DCT of composite length for DCT based transcoder Park, YS; Park, HyunWook, IEEE TRANSACTIONS ON IMAGE PROCESSING, v.15, pp.494 - 500, 2006-02 |
Arbitration latency analysis of the shared channel architecture for high performance multi-master SoC Suh, J.; Yoo, Hoi-Jun, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp.388 - 391, 2004-08-04 |
ARC 코드를 갖는 광 CDMA 시스템의 성능 분석 민성식; 원용협; 김병휘, Photonics Conference 2003, pp.91 - 92, 2003-11 |
Architecting Throughput Processors with New Flash Zhang, Jie; Jung, Myoungsoo, 12TH ANNUAL NON-VOLATILE MEMORIES WORKSHOP, IEEE, 2021-03-07 |
Architecting voltage islands in core-based System-on-a-Chip designs Hu, J; Shin, Youngsoo; Dhanwada, N; Marculescu, R, Int'l Symp. on Low Power Electronics and Design (ISLPED), pp.180 - 185, ACM Press, 2004-08 |
Architectural solution and design of low-power CMOS interrogator with large dynamic range and noise immunity = 매우 넓은 동적 영역을 갖고 잡음에 강인한 저전력 CMOS interrogator 를 위한 구조 제안 및 설계link Kim, Eun-Hee; 김은희; et al, 한국과학기술원, 2012 |
Architectural techniques to reduce DRAM latency = DRAM 레이턴시를 줄이기 위한 아키텍처 연구link Shin, Wongyu; Kim, Lee-Sup; et al, 한국과학기술원, 2017 |
Architectural trade-off of Viterbi Decoder using Modified Register Exchanged State-mapping method Park, Sin Chong, ITC-CSCC 2005, pp.125 - 126, 2005-07-01 |
Architectural workload characterization of javascript language on mobile processor = 자바스크립트 언어의 모바일 프로세서에 대한 아키텍처적 특성 연구link Chang, Gihun; 장기훈; et al, 한국과학기술원, 2014 |
Architecture and algorithm for high precision image rejection and spurious rejection mixers using digital compensation Kim, Y.; Shin, S.; Lee, Kwyro, IEEE MSS-S International Microwave Symposium Digest, pp.799 - 802, IEEE, 2002-06-02 |
Architecture and Algorithm for High Prejection and Spurious Rejection Mixers Using Digital Compensation Lee, Kwyro; Kim, Y.; Shin, S., 2002 IEEE MTT-S, pp.799 - 802, 2002 |
Architecture and algorithm for ultra-high precision image rejection mixer using digital compensation Kim, YJ; Park, HC; Nam, IK; Lee, Kwyro, ELECTRONICS LETTERS, v.36, no.19, pp.1604 - 1606, 2000-09 |
Architecture and algorithm for ultrahigh precision image rejection mixer and spurious rejection mixer using digital compensation = 디지털 보상 회로가 포함된 영상 제거 믹서와 스퓨리어스 제거 믹서를 위한 구조 및 알고리즘link Kim, Young-Jin; 김영진; et al, 한국과학기술원, 2002 |
Architecture and Control Algorithms for Combating Partial Shading in Photovoltaic Systems Wang, Yanzhi; Lin, Xue; Kim, Younghyun; Chang, Naehyuck; Pedram, Massoud, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.33, no.6, pp.917 - 930, 2014-06 |
Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000 Rhu, M.; Park, In-Cheol, 2009 IEEE International Conference on Image Processing, ICIP 2009, pp.2665 - 2668, 2009-11-07 |
Architecture for multi-processor SoC platform using dedicated channels Lee G.; Park, Sin Chong, Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005, v.2005, pp.525 - 529, 2005-07-20 |
Architecture level simulation of IEEE 802.11n MAC using systemc Yoon S.-R.; Park, Sin Chong, 5th IASTED Asian Conference on Communication Systems and Networks, AsiaCSN 2008, pp.46 - 49, 2008-04-02 |
Architecture of broadband personal communication network Kim, Duk Kyung; Lee, Seung Joon; Choi, Dae Woo; Sung, Dan Keun, Proceedings of the 1996 7th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC'96. Part 3 (of 3), v.2, pp.603 - 607, 1996-10-15 |
Architecture of connecting optical PCB, transceiver modules for optical PCB and optical connection block Park, HyoHoon; Hwang, Sung Hwan; Cho, Han Seo; Cho, Mu Hee, 2006-06-13 |
Architecture of Multi Cloud Resource Broker in Cloud Federation Kang, Dong Ki; Kim, Byung Sang; Kim, Seong Hwan; Youn, Chan-Hyun, 2012 International Exposition Yeosu Korea, International Conference on Information Technology(YSEC 2012), v.1, Korea Information Processing Society, 2012-04-27 |
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