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Clock Gating Synthesis of Pulsed-Latch Circuits Paik, Seung-Whun; Han, In-Hak; Kim, Sang-Min; Shin, Young-Soo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.31, no.7, pp.1019 - 1030, 2012-07 |
Pulsed-Latch Aware Placement for Timing-Integrity Optimization Chuang, Yi-Lin; Kim, Sangmin; Shin, Youngsoo; Chang, Yao-Wen, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.12, pp.1856 - 1869, 2011-12 |
Pulsed-Latch-Based ASIC design for high performance and low power = 펄스래치기반 고성능 저전력 ASIC 설계link Paik, Seung-Whun; 백승훈; et al, 한국과학기술원, 2011 |
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