Browse "School of Electrical Engineering(전기및전자공학부)" by Subject jitter

Showing results 1 to 14 of 14

A 250-MHz-2-GHz wide-range delay-locked loop

Kim, BG; Kim, Lee-Supresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, pp.1310 - 1321, 2005-06

A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

Lee, Woo-Jin; Kim, Jae-Min; Ryu, Chung-Hyun; Park, Jong-Bae; Kim, Jun-Chul; Kim, Joung-Horesearcher, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.19, pp.512 - 514, 2009-08

A behavioral modeling approach to the design of a low jitter clock source

Manganaro, G; Kwak, SU; Cho, SeongHwanresearcher; Pulincherry, A, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, v.50, no.11, pp.804 - 814, 2003-11

A Compact and Wide-Band Passive Equalizer Design Using a Stub With Defected Ground Structure for High Speed Data Transmission

Shim, Yu-Jeong; Lee, Woo-Jin; Song, Eak-Hwan; Cho, Jeong-Hyeon; Kim, Joung-Horesearcher, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.20, pp.256 - 258, 2010-05

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

Kim, BG; Kim, Lee-Supresearcher; Park, KI; Jun, YH; Cho, SI; Kim, LS; Jun, YH; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.44, pp.1522 - 1530, 2009-05

A high speed transceiver with a transmitter eliminating crosstalk induced jitter and a receiver with adaptively controllable reference voltage = 크로스톡 지터 제거하는 송신기와 레퍼런스 전압을 적응시키는 수신기를 가지는 고속 송수신기link

Cho, Young-Chul; 조영철; et al, 한국과학기술원, 2008

(A) novel low jitter and skew clock distribution network for 3-D stacked chip package = 3차원 적층 칩 패키지를 위한 새로운 저 지터, 저 스큐 클럭 신호 분배 네트워크link

Lee, Woo-Jin; 이우진; et al, 한국과학기술원, 2011

(A) three-dimensional stacked-chip star-wiring I/O clock distribution networks for low jitter, skew, and delay applications = 저 지터, 저 스큐, 저 디레이를 위한 3차원 적층칩 스타 와이어링 I/O 클럭 분배 네트워크link

Ryu, Chung-hyun; 유충현; et al, 한국과학기술원, 2008

Adaptive cycle extension in multimedia document retrieval

Won, Youjipresearcher; Cho, K, XML-BASED DATA MANAGEMENT AND MULTIMEDIA ENGINEERING-EDBT 2002 WORKSHOPS, v.2490, pp.391 - 405, 2002-03

Adaptive cycle management in soft real-time disk retrieval

Won, Youjipresearcher; Shin, Il-Hoon; Koh, Kern, INFORMATION SYSTEMS, v.31, no.8, pp.832 - 848, 2006-12

Design of low jitter DLL/PLL for on-chip and off-chip synchronizations = 칩 내부 및 칩 외부 동기화를 위한 낮은 지터의 DLL/PLL 설계link

Kim, Byung-Guk; 김병국; et al, 한국과학기술원, 2008

Modeling and Analysis of Simultaneous Switching Noise Effects on Jitter Characteristics of Delay Locked Loop and Serial Link in a Hierarchical System of Chip, Package and PCB = 칩, 패키지, 피씨비로 구성된 시스템에서 동시 스위칭 노이즈가 DLL과 직렬 통신 시스템의 지터 특성에 미치는 영향에 대한 모델링과 분석link

Shim, Yu-Jeong; 심유정; et al, 한국과학기술원, 2011

New Phase-Locked Loop Design: Understanding the Impact of a Phase-Tracking Channel Detector

Lee, Jaewook; Moon, Jaekyunresearcher; Zhang, Tong; Haratsch, Erich F., IEEE TRANSACTIONS ON MAGNETICS, v.46, no.3, pp.830 - 836, 2010-03

On-Chip electromagnetic bandgap structures for suppression of simultaneous switching noise cou-pling in on-chip power distribution networks = 온 칩 전력 분배망에서 동시 스위칭 잡음 간섭을 억제하기 위한 온 칩 전자 밴드갭 구조들link

Hwang, Chul-Soon; 황철순; et al, 한국과학기술원, 2012



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