Browse "School of Electrical Engineering(전기및전자공학부)" by Subject Jitter
Showing results 1 to 17 of 17
| 3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS Yoon, Jong-Hyeok; Kwon, Kyeongha; Bae, Hyeon-Min, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.8, pp.2647 - 2658, 2020-08 |
| A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS Jung, Chongsoo; Lee, Dongil; Kim, Yong-Hun; Lee, Daewoong; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.12, pp.1972 - 1976, 2019-12 |
| A 46-nF/10-M omega Range 114-aF/0.37-omega Resolution Parasitic- and Temperature-Insensitive Reconfigurable RC-to-Digital Converter in 0.18-mu m CMOS George, Arup K.; Shim, Wooyoon; Kung, Jaeha; Kim, Ji-Hoon; Je, Minkyu; Lee, Junghyup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.69, no.3, pp.1171 - 1184, 2022-03 |
| A 7–8.5 GHz LC Voltage-Controlled Oscillator with –111.7 dBc/Hz Phase Noise at 1-MHz offset for Ultra-Low-Jitter Phase-Locked Loop 조용우; 채문재; 최재혁, IDEC Journal of Integrated Circuits and Systems, v.9, no.1, pp.1 - 5, 2023-01 |
| A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M Hwang, Chanwoong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2841 - 2855, 2022-09 |
| A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.1, pp.298 - 309, 2021-01 |
| A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique Lee, Yongsun; Seong, Taeho; Yoo, Seyeon; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1192 - 1202, 2018-04 |
| A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM Jung, Yeonwook; Lee, Seongseop; Kim, Hyojun; Cho, SeongHwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.1, pp.270 - 278, 2023-01 |
| A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.2, pp.480 - 491, 2022-02 |
| An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector Park, Suneui; Choi, Seojin; Yoo, Seyeon; Cho, Yoonseo; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2829 - 2840, 2022-09 |
| An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators Kim, Juyeop; Lim, Younghyun; Yoon, Heein; Lee, Yongsun; Park, Hangi; Cho, Yoonseo; Seong, Taeho; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.12, pp.3466 - 3477, 2019-12 |
| Building an Energy-efficient Uplink and Downlink Delay Aware TDM-PON System Newaz, S.H.Shah; Jang, Min Seok; Mohammed, Alaelddin Fuad Yousif; Lee, Gyu Myoung; Choi, Jun Kyun, OPTICAL FIBER TECHNOLOGY, v.29, pp.34 - 52, 2016-05 |
| Estimation of data-dependent jitter using single pulse analysis method in high-speed interconnects = 단일비트응답 분석을 통한 고속신호 전송선에서의 신호의존지터 예측link Song, Eak-Hwan; 송익환; et al, 한국과학기술원, 2006 |
| Jitter-tolerant I/O clock distribution network using chip and package hybrid interconnection = 칩과 패키지의 혼성 전송선을 이용한 저 지터 입출력 클럭 신호 분배의 설계 및 구현link Chung, Dae-Hyun; 정대현; et al, 한국과학기술원, 2006 |
| Low-noise PLL/DLL design and jitter/phase noise analysis = 저잡음 PLL/DLL 설계 및 지터/위상잡음 분석link Lee, Joon-Suk; 이준석; et al, 한국과학기술원, 2002 |
| Proposal of TSV-based 3D clock distribution networks and analysis = 관통 실리콘 비아 기반 3차원 클락 분배망에 관한 연구link Kim, Da-Young; 김다영; et al, 한국과학기술원, 2012 |
| Timing evaluation of MAC-layer error control on ARM9-based mobile embedded systems Kim, C; Kang, K; Noh, DK; Ryu, J; Ma, JoongSoo, TELECOMMUNICATION SYSTEMS, v.45, pp.329 - 337, 2010-12 |
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