Browse "School of Electrical Engineering(전기및전자공학부)" by Subject CDR
Showing results 1 to 10 of 10
| 3x-oversampling based clock and data recovery in high speed memory interface = 고속 메모리 인터페이스에서의 3배 추가 표본을 이용한 클럭-데이터 복원link Jeon, Younho; Bae, Hyeon-Min; et al, 한국과학기술원, 2017 |
| A 10-Gb/s CDR with an adaptive optimum loop-bandwidth calibrator for serial communication links Lee, Joon Yeong; Yoon, Jonghyeok; Bae, Hyeon-Min, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.8, 2014-08 |
| A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10-and 40-GbE Links Yoon, Taehun; Lee, Joon Yeong; Lee, Jinhee; Han, Kwangseok; Lee, Jeong-Sup; Lee, Sangeun; Kim, Taeho; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.3, pp.688 - 703, 2017-03 |
| A 4 x 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS Lee, Joon Yeong; Yang, Jaehyeok; Yoon, Jong Hyeok; Kwon, Soon Won; Won, Hyosup; Han, Jinho; Bae, Hyeon-Min, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.6, pp.2310 - 2320, 2016-06 |
| A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation Lee, Won-Young; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.59, no.11, pp.2518 - 2528, 2012-11 |
| A low-power high-speed transceiver IC design techniques for NRZ-PAM-4 signaling = NRZ/PAM-4 시그널링을 위한 저전력 고속 트랜시버 IC 설계 기술link Yoon, Taehun; 윤태훈; et al, 한국과학기술원, 2017 |
| An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs Kwon, Soon Won; Lee, Joon Yeong; Lee, Jinhee; Han, Kwangseok; Kim, Taeho; Lee, Sangeun; Lee, Jeong Sup; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.12, pp.2817 - 2828, 2015-12 |
| Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator Han, Jinho; Yang, Jaehyeok; Bae, Hyeon-Min, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.59, no.6, pp.336 - 340, 2012-06 |
| Application of Kalman gain for minimum mean-squared phase-error bound in bang-bang CDRs = 칼만 이득을 적용한 최소 위상 평균제곱오차를 갖는 bang-bang CDR에 대한 연구link Lee, Joon-Yeong; 이준영; et al, 한국과학기술원, 2013 |
| Inter-chip serial link design in CMOS = CMOS를 이용한 칩간 직렬통신기의 설계link Kim, Jin-Wook; 김진욱; et al, 한국과학기술원, 2004 |
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