Browse "School of Electrical Engineering(전기및전자공학부)" by Subject factored form
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| Clock gating synthesis through reusing existing combinational logic = 논리 회로의 재활용을 이용한 클락게이팅의 합성link Han, In-Hak; 한인학; et al, 한국과학기술원, 2012 |
| Simplifying Clock Gating Logic by Matching Factored Forms Han, Inhak; Shin, Youngsoo, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.6, pp.1338 - 1349, 2014-06 |
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