Browse "School of Electrical Engineering(전기및전자공학부)" by Subject GATE
Showing results 1 to 26 of 26
A SONOS device with a separated charge trapping layer for improvement of charge injection Ahn, Jae-Hyuk; Moon, Dong-Il; Ko, Seung-Won; Kim, Chang-Hoon; Kim, Jee-Yeon; Kim, Moon-Seok; Seol, Myeong-Lok; et al, AIP ADVANCES, v.7, no.3, 2017-03 |
| Aligned Circular-Type Nanowire Transistors Grown on Multilayer Graphene Film Kim, Hwansoo; Choi, Hongkyw; Choi, Sung-Yool; Ju, Sanghyun, JOURNAL OF PHYSICAL CHEMISTRY C, v.115, no.45, pp.22163 - 22167, 2011-11 |
| An Optically Assisted Program Method for Capacitorless 1T-DRAM Moon, Dong-Il; Choi, Sung-Jin; Han, Jin-Woo; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.57, no.7, pp.1714 - 1718, 2010-07 |
| Analysis of Transconductance (g(m)) in Schottky-Barrier MOSFETs Choi, Sung-Jin; Choi, Chel-Jong; Kim, Jee-Yeon; Jang, Moon-Gyu; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.58, no.2, pp.427 - 432, 2011-02 |
| Comprehensive Study on the Relation Between Low-Frequency Noise and Asymmetric Parasitic Resistances in a Vertical Pillar-Type FET Lee, Seung-Wook; Bang, Tewook; Kim, Choong-Ki; Hwang, Kyu-Man; Jang, Byung Chul; Moon, Dong-Il; Bae, Hagyoul; et al, IEEE ELECTRON DEVICE LETTERS, v.38, no.8, pp.1008 - 1011, 2017-08 |
| Designed Workfunction Engineering of Double-Stacked Metal Nanocrystals for Nonvolatile Memory Application Ryu, Seong-Wan; Lee, Jong-Won; Han, Jin-Woo; Kim, Sung-Ho; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.56, no.3, pp.377 - 382, 2009-03 |
| Effect of channel orientation in p-type nanowire Schottky barrier metal-oxide-semiconductor field-effect transistors Shin, Mincheol, APPLIED PHYSICS LETTERS, v.97, no.9, pp.092108, 2010-08 |
| Electron mobility enhancement using ultrathin pure Ge on Si substrate Yeo, CC; Cho, Byung Jin; Gao, E; Lee, SJ; Lee, AH; Yu, CY; Liu, CW; et al, IEEE ELECTRON DEVICE LETTERS, v.26, no.10, pp.761 - 763, 2005-10 |
| Experimental analysis of multi-lambda injection locking in single mode Fabry-Perot laser diode Nakarmi, Bikash; Zhang, Xuping; Won, Yong Hyub, OPTICS COMMUNICATIONS, v.358, pp.24 - 29, 2015-09 |
| Extremely scaled silicon nano-CMOS devices Chang, LL; Choi, Yang-Kyu; Ha, DW; Ranade, P; Xiong, SY; Bokor, J; Hu, CM; et al, PROCEEDINGS OF THE IEEE, v.91, no.11, pp.1860 - 1873, 2003-11 |
| Functionalized Graphene as an Ultrathin Seed Layer for the Atomic Layer Deposition of Conformal High-k Dielectrics on Graphene Shin, Woocheol; Bong, Jae Hoon; Choi, Sung-Yool; Cho, Byung Jin, ACS APPLIED MATERIALS INTERFACES, v.5, no.22, pp.11515 - 11519, 2013-11 |
| Graphene-based photonic devices for soft hybrid optoelectronic systems Kim, Jin Tae; Kim, Jaehyeon; Choi, Hongkyw; Choi, Choon-Gi; Choi, Sung-Yool, NANOTECHNOLOGY, v.23, no.34, 2012-08 |
| Improved Drain Current Saturation and Voltage Gain in Graphene-on-Silicon Field Effect Transistors Song, Seung-Min; Bong, Jae Hoon; Hwang, Wan Sik; Cho, Byung-Jin, SCIENTIFIC REPORTS, v.6, 2016-05 |
| Investigation of Leaky Characteristic in a Single-Transistor-Based Leaky Integrate-and-Fire Neuron Han, Joon-Kyu; Kim, Myung-Su; Kim, Seung-Il; Lee, Mun-Woo; Lee, Sang-Won; Yu, Ji-Man; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.68, no.11, pp.5912 - 5915, 2021-11 |
| Mechanical Stability Analysis via Neutral Mechanical Plane for High-Performance Flexible Si Nanomembrane FDSOI Device Kim, Seung-Yoon; Bong, Jae Hoon; Kim, Cheolgyu; Hwang, Wan Sik; Kim, Taek-Soo; Cho, Byung Jin, ADVANCED MATERIALS INTERFACES, v.4, no.21, 2017-11 |
| MOS characteristics of synthesized HfAlON-HfO2 stack using AIN-HfO2 Park, CS; Cho, Byung Jin; Kwong, DL, IEEE ELECTRON DEVICE LETTERS, v.25, no.9, pp.619 - 621, 2004-09 |
| Nanometer-Scale Oxide Thin Film Transistor with Potential for High-Density Image Sensor Applications Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; et al, ACS APPLIED MATERIALS & INTERFACES, v.3, no.1, pp.1 - 6, 2011-01 |
| Nanowire FET Biosensors on a Bulk Silicon Substrate Ahn, Jae-Hyuk; Kim, Jee-Yeon; Choi, Kyung-Yong; Moon, Dong-Il; Kim, Chang-Hoon; Seol, Myeong-Lok; Park, Tae-Jung; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.59, no.8, pp.2243 - 2249, 2012-08 |
| Non-Volatile Majority Function Logic Using Ferroelectric Memory for Logic in Memory Technology Hwang, Junghyeon; Lim, Sehee; Kim, Giuk; Jung, Seong-Ook; Jeon, Sanghun, IEEE ELECTRON DEVICE LETTERS, v.43, no.7, pp.1049 - 1052, 2022-07 |
| Off-state leakage in MOSFET considering source/drain extension regions Hur, Jae; Jeong, Woo Jin; Shin, Mincheol; Choi, Yang-Kyu, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, v.36, no.8, pp.085018, 2021-08 |
| One Biristor-Two Transistor (1B2T) Neuron With Reduced Output Voltage and Pulsewidth for Energy-Efficient Neuromorphic Hardware Han, Joon-Kyu; Yun, Gyeong-Jun; Han, Seong-Joo; Yu, Ji-Man; Choi, Yang-Kyu, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.68, no.1, pp.430 - 433, 2021-01 |
| p-Type Nanowire Schottky Barrier MOSFETs: Comparative Study of Ge- and Si-Channel Devices Choi, Won Chul; Lee, Jaehyun; Shin, Mincheol, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.61, no.1, pp.37 - 43, 2014-01 |
| Performance Assessment of III-V Channel Ultra-Thin-Body Schottky-Barrier MOSFETs Lee, Jaehyun; Shin, Mincheol, IEEE ELECTRON DEVICE LETTERS, v.35, no.7, pp.726 - 728, 2014-07 |
| Resistance analysis and device design guideline for graphene RF transistors Hong, Seul Ki; Jeon, Sang Chul; Hwang, Wan Sik; Cho, Byung Jin, 2D MATERIALS, v.2, no.3, 2015-07 |
| Simulation Study of Germanium p-Type Nanowire Schottky Barrier MOSFETs Lee, Jaehyun; Shin, Mincheol, IEEE ELECTRON DEVICE LETTERS, v.34, no.3, pp.342 - 344, 2013-03 |
| Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor Lee, Dong-Il; Lee, Byung-Hyun; Yoon, Jinsu; Ahn, Dae-Chul; Park, Jun-Young; Hur, Jae; Kim, Myung-Su; et al, ACS NANO, v.10, no.12, pp.10894 - 10900, 2016-12 |
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