Browse "School of Electrical Engineering(전기및전자공학부)" by Subject DRAM chips

Showing results 1 to 3 of 3

1
A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F(2) cell

Kim, JS; Choi, YS; Yoo, Hoi-Junresearcher; Seo, KS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.33, no.7, pp.1096 - 1102, 1998-07

2
A study of pipeline architectures for high-speed synchronous DRAMs

Yoo, Hoi-Junresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.32, no.10, pp.1597 - 1603, 1997-10

3
High speed latchup resistant CMOS data output buffer for submicrometre DRAM application

Yoo, Hoi-Junresearcher, ELECTRONICS LETTERS, v.32, no.24, pp.2229 - 2230, 1996-11

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